# Logic circuit rule set optimized for minimal transition rules, at the
# cost of physical space and readability. AND, OR, XOR, and NOT gates have
# been replaced by the NOR gate, and sync  and 3-output fan gates have been
# removed.
#
# Gates lock during computation, allowing sequential gate logic.


### WIRE RULES
### 2 rules, 3 species
# Move
(1) 0 + B -> B + 0
(1) 1 + B -> B + 1


### NOR GATE
### 14 rules, 18 species
# Load
(1) 0 + BRx -> B + 0Rx
(1) 1 + BRx -> B + 1Rx
(1) 0 + BRy -> B + 0Ry
(1) 1 + BRy -> B + 1Ry
(1) 0Rx + BRz -> HRx + 0Rz
(1) 1Rx + BRz -> HRx + 1Rz
# Logic rules
(1) 0Ry + 0Rz -> HRy + 1Rk
(1) 0Ry + 1Rz -> HRy + 0Rk
(1) 1Ry + 0Rz -> HRy + 0Rk
(1) 1Ry + 1Rz -> HRy + 0Rk
# Unload
(1) 0Rk + B -> RRRz + 0
(1) 1Rk + B -> RRRz + 1
# Reset
(1) RRRz + HRx -> RRz + BRx
(1) RRz + HRy -> BRz + BRy


### 2-FAN-OUT
### 10 rules, 11 species
# Load
(1) 0 + BF -> B + 0F
(1) 1 + BF -> B + 1F
# "Logic"
(1) 0F + BFx -> 0f + 0Fx
(1) 1F + BFx -> 1f + 1Fx
(1) 0f + BFy -> BF + 0Fy
(1) 1f + BFy -> BF + 1Fy
# Unload
(1) 0Fx + B -> BFx + 0
(1) 1Fx + B -> BFx + 1
(1) 0Fy + B -> BFy + 0
(1) 1Fy + B -> BFy + 1

### WIRE CROSS
### 20 rules, 19 species
# Load
(1) 0 + BCx -> B + 0Cx
(1) 1 + BCx -> B + 1Cx
(1) 0 + BCy -> B + 0Cy
(1) 1 + BCy -> B + 1Cy
# Signal push to center
(1) 0Cx + BC -> HCx + 0Cx
(1) 1Cx + BC -> HCx + 1Cx
(1) 0Cy + BC -> HCy + 0Cy
(1) 1Cy + BC -> HCy + 1Cy
# Signal push to output
(1) 0Cx + BCw -> BC + 0Cw
(1) 1Cx + BCw -> BC + 1Cw
(1) 0Cy + BCz -> BC + 0Cz
(1) 1Cy + BCz -> BC + 1Cz
# Unload
(1) 0Cw + B -> RCw + 0
(1) 1Cw + B -> RCw + 1
(1) 0Cz + B -> RCz + 0
(1) 1Cz + B -> RCz + 1
# Reset
(1) RCw + BC -> BCw + RCcw
(1) RCcw + HCx -> BC + BCx
(1) RCz + BC -> BCz + RCcz
(1) RCcz + HCy -> BC + BCy

## ^ 46 rules, 51 species ^ ##